Pascal Giard, P.Eng., Ph.D.
Full Professor of Electrical Engineering at École de technologie supérieure (ETS), a member of the Université du Québec network.
I am actively looking for talented students interested in hardware implementation autogeneration, error detection and correction, compiler design, ... Have a look at the Open Positions.
Biography
I received my B.Eng. and M.Eng. degrees in electrical engineering from the École de technologie supérieure (ÉTS), Montréal, Canada, in 2006 and 2009, respectively, and the Ph.D. degree from McGill University, Montréal, Canada, in 2016.
From 2009 to 2010, I worked as a research professional in the NSERC – Ultra Electronics Chair in Wireless Emergency and Tactical Communications at ÉTS. From 2007 to 2016, I was a Lecturer in the Department of Electrical Engineering at ÉTS. I also collaborated as a research professional in the Research Chair in Design Methodology for Highly Integrated and Reliable Hybrid Systems (CRICSH) at ÉTS from 2012 to 2016. From 2016 to 2018, I worked with Prof. Andreas Burg as a Postdoctoral Researcher at the Telecommunication Circuits Laboratory (TCL), École polytechnique fédérale de Lausanne (EPFL), Switzerland.
I am currently an Full Professor in the Electrical Engineering Department of the École de technologie supérieure (ÉTS), Montréal, Canada. I joined ÉTS as an Associate Professor in late August 2018, and was promoted to Full Professor in June 2026. I was a Visiting Professor at Rheinland-Pfälzische Technische Universität (RPTU), Kaiserslautern, Germany, in June 2025, at ENSEIRB-MATMECA, Bordeaux INP, Bordeaux, France, in November 2025, and at Eindhoven University of Technology (TU/e), Eindhoven, The Netherlands, in March 2026 and again in August 2026. My stay in Bordeaux was funded through a competitive call of the Université de Bordeaux (Visiting Professors/Researchers Program 2025), and my August 2026 stay at TU/e was funded by QDNL. My research interests are in the design and implementation of signal processing systems with a focus on embedded systems, connected objects, and modern error-correcting codes.
I received the Best Experimental-Demonstration Award at the IEEE CASS & ReSMiQ Innovation Day 2015. I serve as a reviewer for several IEEE journals and conferences, and served as an Associate Editor for the Elsevier MicroElectronics Journal (MEJ) from 2016 to 2020. Since August 2021, I have been serving as an Associate Editor for the Coding area of IEEE Communications Letters. I am also Technical Program Co-Chair of the IEEE International Workshop on Signal Processing Systems (IEEE SiPS 2026), which will be held in Bordeaux, France.
News & Travel
- Aug 2026:
- Our paper that proposes a low-complexity approach for the automorphism ensemble decoder using successive cancellation as constituent decoders has been accepted for publication in IEEE Communications Letters.
- Olivier JUTEAU-DESJARDINS successfully defended his master’s thesis. Congratulations Olivier!
- In Eindhoven, The Netherlands, as a Visiting Professor at TU/e, working with Profs. Alexios BALATSOUKAS-STIMMING and Alex ALVARADO. This stay was funded by QDNL.
- Jun 2026: Promoted to Full Professor in the Electrical Engineering Department of ÉTS, after nearly eight years as an Associate Professor.
- May 2026:
- Anis CHABI joined the group as a research master student to work on the system integration of a hardware accelerator for the Ethereum Virtual Machine. Welcome Anis!
- Paul BOSSEBOEUF joined the group as an undergrad research intern to work on a communication interface with a hybrid Ethereum/Bitcoin cold wallet implemented on FPGA. Welcome Paul!
- Mar 2026:
- In Eindhoven, The Netherlands, as a Visiting Professor at TU/e, working with Profs. Alexios BALATSOUKAS-STIMMING and Alex ALVARADO.
- Our paper that explores the potential of a radio acoustical virtual environment through a mockup, that incorporates key algorithms, evaluated on participants has been published in the Journal of the Acoustical Society of America.
- Dec 2025: Joel Poncha LEMAYIAN successfully defended his PhD thesis. Congratulations Poncha!
- Nov 2025:
- Our paper that proposes EthVault, a secure, resource-conscious FPGA-based Ethereum cold wallet, has been accepted for publication in IET Blockchain.
- Our paper that introduces EVMx, an FPGA-based accelerator for smart-contract processing, is now published in IEEE TVLSI. We also released the full implementation as open hardware (CERN-OHL-W-2.0). EVMx introduces a custom FPGA architecture that significantly speeds up and improves the energy efficiency of Ethereum smart-contract execution.
- In Bordeaux, France, as a Visiting Professor at ENSEIRB-MATMECA, Bordeaux INP, working with Profs. Camille LEROUX and Christophe JÉGO. This stay was funded through a competitive call of the Université de Bordeaux (Visiting Professors/Researchers Program 2025).
- Oct 2025: Our paper that proposes partitioned successive-cancellation list flip decoding of polar codes with early stopping and fast restart mechanisms has been published in the Springer Journal of Signal Processing Systems.